diff --git a/boards/nanorp2040connect.json b/boards/nanorp2040connect.json index 95d684b..4e9c594 100644 --- a/boards/nanorp2040connect.json +++ b/boards/nanorp2040connect.json @@ -48,7 +48,8 @@ "cmsis-dap", "jlink", "raspberrypi-swd", - "picotool" + "picotool", + "picoprobe" ] }, "url": "https://blog.arduino.cc/2021/01/20/welcome-raspberry-pi-to-the-world-of-microcontrollers/", diff --git a/boards/pico.json b/boards/pico.json index 2587285..6176e7e 100644 --- a/boards/pico.json +++ b/boards/pico.json @@ -44,7 +44,8 @@ "cmsis-dap", "jlink", "raspberrypi-swd", - "picotool" + "picotool", + "picoprobe" ] }, "url": "https://www.raspberrypi.org/products/raspberry-pi-pico/", diff --git a/builder/main.py b/builder/main.py index 34b5595..178c622 100644 --- a/builder/main.py +++ b/builder/main.py @@ -356,15 +356,25 @@ elif upload_protocol in debug_tools: openocd_args.extend( ["-c", "adapter speed %s" % env.GetProjectOption("debug_speed")] ) - openocd_args.extend([ - "-c", "program {$SOURCE} %s verify reset; shutdown;" % - board.get("upload.offset_address", "") - ]) + if "uploadfs" in COMMAND_LINE_TARGETS: + # filesystem upload. use FS_START. + openocd_args.extend([ + "-c", "program {$SOURCE} ${hex(FS_START)} verify reset; shutdown;" + ]) + else: + # normal firmware upload. flash starts at 0x10000000 + openocd_args.extend([ + "-c", "program {$SOURCE} %s verify reset; shutdown;" % + board.get("upload.offset_address", "0x10000000") + ]) openocd_args = [ f.replace("$PACKAGE_DIR", platform.get_package_dir( "tool-openocd-raspberrypi") or "") for f in openocd_args ] + # use ELF file for upload, not bin (target_firm). otherwise needs + # offset 0x10000000 + #upload_source = target_elf env.Replace( UPLOADER="openocd", UPLOADERFLAGS=openocd_args, diff --git a/misc/svd/rp2040.svd b/misc/svd/rp2040.svd index 9d44dd1..f600d47 100644 --- a/misc/svd/rp2040.svd +++ b/misc/svd/rp2040.svd @@ -24673,25 +24673,6 @@ I2C Interrupt Status Register\n\n Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register. - - read-only - [13:13] - See IC_RAW_INTR_STAT for a detailed description of R_MASTER_ON_HOLD bit.\n\n - Reset value: 0x0 - - - R_MASTER_ON_HOLD interrupt is inactive - INACTIVE - 0 - - - R_MASTER_ON_HOLD interrupt is active - ACTIVE - 1 - - - R_MASTER_ON_HOLD - read-only [12:12] @@ -24948,25 +24929,6 @@ I2C Interrupt Mask Register.\n\n These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt. - - read-only - [13:13] - This M_MASTER_ON_HOLD_read_only bit masks the R_MASTER_ON_HOLD interrupt in IC_INTR_STAT register.\n\n - Reset value: 0x0 - - - MASTER_ON_HOLD interrupt is masked - ENABLED - 0 - - - MASTER_ON_HOLD interrupt is unmasked - DISABLED - 1 - - - M_MASTER_ON_HOLD_READ_ONLY - read-write [12:12] @@ -25223,25 +25185,6 @@ I2C Raw Interrupt Status Register\n\n Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c. - - read-only - [13:13] - Indicates whether master is holding the bus and TX FIFO is empty. Enabled only when I2C_DYNAMIC_TAR_UPDATE=1 and IC_EMPTYFIFO_HOLD_MASTER_EN=1.\n\n - Reset value: 0x0 - - - MASTER_ON_HOLD interrupt is inactive - INACTIVE - 0 - - - MASTER_ON_HOLD interrupt is active - ACTIVE - 1 - - - MASTER_ON_HOLD - read-only [12:12] @@ -25931,7 +25874,7 @@ The bits [15:0] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW).\n\n The bits [23:16] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode.\n\n Writes to this register succeed only when IC_ENABLE[0]=0.\n\n - The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode one cycle in master mode, seven cycles in slave mode for the value to be implemented.\n\n + The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented.\n\n The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles. @@ -29321,7 +29264,7 @@ set to 0xaa0 + div where\n div = 0 divides by 32\n div = 1-31 divides by div\n - any other value sets div=0 and therefore divides by 32\n + any other value sets div=31\n this register resets to div=16 @@ -29342,7 +29285,7 @@ read-write [11:4] - set to 0xaa0\n + set to 0xaa\n any other value enables the output with shift=0 PASSWD @@ -29385,7 +29328,7 @@ read-write [24:24] - An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FRFEQA or FREQB or DORMANT + An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT oneToClear BADWRITE @@ -33630,6 +33573,5613 @@ 32 1 + + + 0 + 0x0100 + registers + + 0x50100000 + DPRAM layout for USB device. + USBCTRL_DPRAM + + + 0x0000 + Bytes 0-3 of the SETUP packet from the host. + + + read-write + [31:16] + WVALUE + + + read-write + [15:8] + BREQUEST + + + read-write + [7:0] + BMREQUESTTYPE + + + SETUP_PACKET_LOW + 0x00000000 + + + 0x0004 + Bytes 4-7 of the setup packet from the host. + + + read-write + [31:16] + WLENGTH + + + read-write + [15:0] + WINDEX + + + SETUP_PACKET_HIGH + 0x00000000 + + + 0x0008 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP1_IN_CONTROL + 0x00000000 + + + 0x000c + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP1_OUT_CONTROL + 0x00000000 + + + 0x0010 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP2_IN_CONTROL + 0x00000000 + + + 0x0014 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP2_OUT_CONTROL + 0x00000000 + + + 0x0018 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP3_IN_CONTROL + 0x00000000 + + + 0x001c + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP3_OUT_CONTROL + 0x00000000 + + + 0x0020 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP4_IN_CONTROL + 0x00000000 + + + 0x0024 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP4_OUT_CONTROL + 0x00000000 + + + 0x0028 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP5_IN_CONTROL + 0x00000000 + + + 0x002c + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP5_OUT_CONTROL + 0x00000000 + + + 0x0030 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP6_IN_CONTROL + 0x00000000 + + + 0x0034 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP6_OUT_CONTROL + 0x00000000 + + + 0x0038 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP7_IN_CONTROL + 0x00000000 + + + 0x003c + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP7_OUT_CONTROL + 0x00000000 + + + 0x0040 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP8_IN_CONTROL + 0x00000000 + + + 0x0044 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP8_OUT_CONTROL + 0x00000000 + + + 0x0048 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP9_IN_CONTROL + 0x00000000 + + + 0x004c + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP9_OUT_CONTROL + 0x00000000 + + + 0x0050 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP10_IN_CONTROL + 0x00000000 + + + 0x0054 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP10_OUT_CONTROL + 0x00000000 + + + 0x0058 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP11_IN_CONTROL + 0x00000000 + + + 0x005c + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP11_OUT_CONTROL + 0x00000000 + + + 0x0060 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP12_IN_CONTROL + 0x00000000 + + + 0x0064 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP12_OUT_CONTROL + 0x00000000 + + + 0x0068 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP13_IN_CONTROL + 0x00000000 + + + 0x006c + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP13_OUT_CONTROL + 0x00000000 + + + 0x0070 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP14_IN_CONTROL + 0x00000000 + + + 0x0074 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP14_OUT_CONTROL + 0x00000000 + + + 0x0078 + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP15_IN_CONTROL + 0x00000000 + + + 0x007c + + + read-write + [31:31] + Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set. + ENABLE + + + read-write + [30:30] + This endpoint is double buffered. + DOUBLE_BUFFERED + + + read-write + [29:29] + Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF + + + read-write + [28:28] + Trigger an interrupt each time both buffers are done. Only valid in double buffered mode. + INTERRUPT_PER_DOUBLE_BUFF + + + read-write + [27:26] + + + Control + 0 + + + Isochronous + 1 + + + Bulk + 2 + + + Interrupt + 3 + + + ENDPOINT_TYPE + + + read-write + [17:17] + Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL + + + read-write + [16:16] + Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK + + + read-write + [15:0] + 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM. + BUFFER_ADDRESS + + + EP15_OUT_CONTROL + 0x00000000 + + + 0x0080 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 1. + LENGTH_0 + + + EP0_IN_BUFFER_CONTROL + 0x00000000 + + + 0x0084 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 1. + LENGTH_0 + + + EP0_OUT_BUFFER_CONTROL + 0x00000000 + + + 0x0088 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 1. + LENGTH_0 + + + EP1_IN_BUFFER_CONTROL + 0x00000000 + + + 0x008c + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 1. + LENGTH_0 + + + EP1_OUT_BUFFER_CONTROL + 0x00000000 + + + 0x0090 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 1. + LENGTH_0 + + + EP2_IN_BUFFER_CONTROL + 0x00000000 + + + 0x0094 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 1. + LENGTH_0 + + + EP2_OUT_BUFFER_CONTROL + 0x00000000 + + + 0x0098 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 1. + LENGTH_0 + + + EP3_IN_BUFFER_CONTROL + 0x00000000 + + + 0x009c + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 1. + LENGTH_0 + + + EP3_OUT_BUFFER_CONTROL + 0x00000000 + + + 0x00a0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 1. + LENGTH_0 + + + EP4_IN_BUFFER_CONTROL + 0x00000000 + + + 0x00a4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 1. + LENGTH_0 + + + EP4_OUT_BUFFER_CONTROL + 0x00000000 + + + 0x00a8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 1. + LENGTH_0 + + + EP5_IN_BUFFER_CONTROL + 0x00000000 + + + 0x00ac + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 1. + LENGTH_0 + + + EP5_OUT_BUFFER_CONTROL + 0x00000000 + + + 0x00b0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 1. + LENGTH_0 + + + EP6_IN_BUFFER_CONTROL + 0x00000000 + + + 0x00b4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 1. + LENGTH_0 + + + EP6_OUT_BUFFER_CONTROL + 0x00000000 + + + 0x00b8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 1. + LENGTH_0 + + + EP7_IN_BUFFER_CONTROL + 0x00000000 + + + 0x00bc + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 1. + LENGTH_0 + + + EP7_OUT_BUFFER_CONTROL + 0x00000000 + + + 0x00c0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 1. + LENGTH_0 + + + EP8_IN_BUFFER_CONTROL + 0x00000000 + + + 0x00c4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 1. + LENGTH_0 + + + EP8_OUT_BUFFER_CONTROL + 0x00000000 + + + 0x00c8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 1. + LENGTH_0 + + + EP9_IN_BUFFER_CONTROL + 0x00000000 + + + 0x00cc + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 1. + LENGTH_0 + + + EP9_OUT_BUFFER_CONTROL + 0x00000000 + + + 0x00d0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 1. + LENGTH_0 + + + EP10_IN_BUFFER_CONTROL + 0x00000000 + + + 0x00d4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 1. + LENGTH_0 + + + EP10_OUT_BUFFER_CONTROL + 0x00000000 + + + 0x00d8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 1. + LENGTH_0 + + + EP11_IN_BUFFER_CONTROL + 0x00000000 + + + 0x00dc + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 1. + LENGTH_0 + + + EP11_OUT_BUFFER_CONTROL + 0x00000000 + + + 0x00e0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 1. + LENGTH_0 + + + EP12_IN_BUFFER_CONTROL + 0x00000000 + + + 0x00e4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 1. + LENGTH_0 + + + EP12_OUT_BUFFER_CONTROL + 0x00000000 + + + 0x00e8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 1. + LENGTH_0 + + + EP13_IN_BUFFER_CONTROL + 0x00000000 + + + 0x00ec + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 1. + LENGTH_0 + + + EP13_OUT_BUFFER_CONTROL + 0x00000000 + + + 0x00f0 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 1. + LENGTH_0 + + + EP14_IN_BUFFER_CONTROL + 0x00000000 + + + 0x00f4 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 1. + LENGTH_0 + + + EP14_OUT_BUFFER_CONTROL + 0x00000000 + + + 0x00f8 + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 1. + LENGTH_0 + + + EP15_IN_BUFFER_CONTROL + 0x00000000 + + + 0x00fc + Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\n + Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode. + + + read-write + [31:31] + Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_1 + + + read-write + [30:30] + Buffer 1 is the last buffer of the transfer. + LAST_1 + + + read-write + [29:29] + The data pid of buffer 1. + PID_1 + + + read-write + [28:27] + The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\n + For a non Isochronous endpoint the offset is always 64 bytes. + + + 128 + 0 + + + 256 + 1 + + + 512 + 2 + + + 1024 + 3 + + + DOUBLE_BUFFER_ISO_OFFSET + + + read-write + [26:26] + Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_1 + + + read-write + [25:16] + The length of the data in buffer 1. + LENGTH_1 + + + read-write + [15:15] + Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data. + FULL_0 + + + read-write + [14:14] + Buffer 0 is the last buffer of the transfer. + LAST_0 + + + read-write + [13:13] + The data pid of buffer 0. + PID_0 + + + read-write + [12:12] + Reset the buffer selector to buffer 0. + RESET + + + read-write + [11:11] + Reply with a stall (valid for both buffers). + STALL + + + read-write + [10:10] + Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back. + AVAILABLE_0 + + + read-write + [9:0] + The length of the data in buffer 1. + LENGTH_0 + + + EP15_OUT_BUFFER_CONTROL + 0x00000000 + + + 32 + 1 + 0 diff --git a/platform.py b/platform.py index 7234899..9da4df1 100644 --- a/platform.py +++ b/platform.py @@ -85,7 +85,7 @@ class RaspberrypiPlatform(PlatformBase): if "tools" not in debug: debug["tools"] = {} - for link in ("cmsis-dap", "jlink", "raspberrypi-swd"): + for link in ("cmsis-dap", "jlink", "raspberrypi-swd", "picoprobe"): if link not in upload_protocols or link in debug["tools"]: continue